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  2 BIT MULTIPLIER: VHDL CODE   Design of 2 bit Multiplier:   library ieee; use ieee.std_logic_1164.all;   entity AND2 is port( A,B: in BIT; x : out BIT); end AND2;   architecture behavioral of AND2 is begin x <= A and B; end behavioral;   entity half_adder is port (a, b : in BIT; sum, carry : out BIT ); end half_adder;   architecture arch of half_adder is begin sum <= a xor b; carry <= a and b; end arch;   entity multiply_struct is port (A, B : in bit_vector(1 downto 0); P : buffer bit_vector(3 downto 0) ); end multiply_struct;   architecture structural of multiply_struct is component AND2 port( A,B: in BIT; X : out BIT); end component;   component half_adder port (A, B : in BIT; sum, carry : out BIT); end component; signal S1,S2,S3,S4:BIT;   begin A1: AND2 port map(A(0),B(0),P(0)); A2: AND2 port map(A(1),B(0),S1); A3: AND2 port map(A(0),B(1),S2); A4: AND2 port map(A(1),B

  INTRODUCTION The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 4 bit ALU which accepts two 4 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into net list (a textual descripti