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Showing posts with the label Verilog Code VHDL ALU 4-bit ALU Arithmatic Logical Unit Arithmatic Logical Calculator Report for ALU Output of ALU

Design and Implementation of 4-Bit Arithmetic Logic Calculator

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  INTRODUCTION The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 4 bit ALU which accepts two 4 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations that we dealt with, are arithmetical, logical and relational. Arithmetic operations include arithmetic addition, subtraction, multiplication and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and result in output logically operated. The operations like the greater than, less than, equal to, exponential etc are also included. To implement ALU, the coding was written in VHDL . The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. Synthesis translates VHDL code into net list (a textual descripti