Design and Implementation of 4-Bit Arithmetic Logic Calculator
INTRODUCTION
The main objective of project is to
design and verify different operations of Arithmetic and Logical Unit (ALU). We
have designed an 4 bit ALU which accepts two 4 bits numbers and the code corresponding
to the operation which it has to perform from the user. The ALU performs the
desired operation and generates the result accordingly. The different
operations that we dealt with, are arithmetical, logical and relational.
Arithmetic operations include arithmetic addition, subtraction, multiplication
and division. Logical operations include AND, OR, NAND, XOR, NOT and NOR. These
take two binary inputs and result in output logically operated. The operations
like the greater than, less than, equal to, exponential etc are also included.
To implement ALU, the coding was written in VHDL . The waveforms were obtained
successfully. After the coding was done, the synthesis of the code was
performed using Xilinx-ISE. Synthesis translates VHDL code into net list (a
textual description). Thereafter, the simulation was done to verify the
synthesized code.
Arithmatic Logic
Unit(ALU)
The ALU, or the arithmetic and logic unit, is
the section of the processor that is involved with executing operations of an
arithmetic or logical nature. In ECL, TTL and CMOS, there are available
integrated packages which are referred to as arithmetic and logic units (ALU).
The logic circuitry in this units is entirely combinational (i.e. consists of
gates with no feedback and no flipflops).The ALU is an extremely versatile and
useful device since, it makes available, in single
package, facility for performing many different
logical and arithmetic operations.
Arithmetic and logic unit consists of two blocks
for different operations
a. Arithmetic operations.
b. Logical operations.
Arithmatic Operations:
These two tasks are performed by constructs of
logic gates, such as half adders and
full adders. While they may be termed 'adders',
with the aid of they can also perform subtraction via use of inverters and
'two's complement'
arithmetic. A binary adder-subtractor is a
combinational circuit that performs the arithmetic operations of addition and
subtraction with binary numbers. Connecting n full adders in cascade produces a
binary adder for two n-bit numbers.
Further logic gate s are used within the ALU to perform a number of different logical tests, including seeing if an operation produces a result of zero. Most of these logical tests are used to then change the values stored in the flag register, so that they may be checked later by separate operations or instructions. Others produce a result which is then stored, and used later in further processing.
BLOCK DIAGRAM
·
The selection lines SEL select the
function ALU performs. These selection lines combined with the input arguments
and desired functions a Instruction Set can be formed.
·
These Instructions can used to create meaningful
programs. Since these are required to be easily available they can be stored
on ROM unit.
·
The input arguments A and B are
often stored in Internal Registers. These along with other special
purpose register form the registers of the microcontroller.
·
ROM memories are slower in speed, hence an intermediate
high speed RAM is often used.
·
All the critical timings, decoding of the instructions
are often grouped together in seperate control and timings unit'
·
If a Micro controller would be constructed only from ALU,
RAM, ROM there would not be any external interface. Hence we have Input/Output IO
ports.
·
Additional features such as 'Interrupts,
communication protocols, EEPROM, Timers/Counters, Debug interfaces etc are
incorporated to make a controller complete.
Truth Table:
The
arithmetic and logic unit simply performs operations on the data given at input
a & input b according to select input sel given by the user.
|
|
SELECTOR LINES |
|
OUTPUT |
|
|
S0 |
S1 |
S2 |
S3 |
F |
|
0 |
0 |
0 |
0 |
A+B |
|
0 |
0 |
0 |
1 |
A-B |
|
0 |
0 |
1 |
0 |
A*B |
|
0 |
0 |
1 |
1 |
A /B |
|
0 |
1 |
0 |
0 |
A <<1 |
|
0 |
1 |
0 |
1 |
A >>1 |
|
0 |
1 |
1 |
0 |
Rotate Left |
|
0 |
1 |
1 |
1 |
Rotate right |
|
1 |
0 |
0 |
0 |
A & B |
|
1 |
0 |
0 |
1 |
A | B |
|
1 |
0 |
1 |
0 |
A ^ B |
|
1 |
0 |
1 |
1 |
A nor B |
|
1 |
1 |
0 |
0 |
A nand B |
|
1 |
1 |
0 |
1 |
A xnor B |
|
1 |
1 |
1 |
0 |
A>B |
|
1 |
1 |
1 |
1 |
A == B |
VERILOG
PROGRAM FOR 4 BIT DIGITAL CALCULATOR
Design Code:
module
alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule
Testbench Code:
module
tb_alu;
//Inputs
reg[7:0] A,B;
reg[3:0] ALU_Sel;
//Outputs
wire[7:0] ALU_Out;
wire CarryOut;
// Verilog code for ALU
integer i;
alu test_unit(
A,B, // ALU 8-bit Inputs
ALU_Sel,// ALU Selection
ALU_Out, // ALU 8-bit Output
CarryOut // Carry Out Flag
);
initial begin
// hold reset state for 100 ns.
A = 8'h0A;
B = 4'h02;
ALU_Sel = 4'h0;
for (i=0;i<=15;i=i+1)
begin
ALU_Sel = ALU_Sel + 8'h01;
#10;
end;
A = 8'hF6;
B = 8'h0A;
end
endmodule
Project Properties:
|
Sr. No. |
Name |
Specification |
|
1. |
Family |
Spartan 6 |
|
2. |
Device |
XC6SLX16 |
|
3. |
Package |
CSG324 |
|
4. |
Top-level Source Type |
HDL |
|
5. |
Synthesis tool |
XST (Verilog) |
|
6. |
Simulator |
ISE Simulator (Verilog) 14.5 |
|
7. |
Preferred Language
|
Verilog |
RTL SCHEMATICS
RESULTS
Figure 1:
Figure 2:
Figure 3:
SYNTHESIS REPORT
|
Selected Device |
6slx16csg324-3 |
Utilization |
|
No. of slice LUTs |
108 out of 9112 |
1% |
|
No. used as Logic |
108 out of 9112 |
1% |
|
No. of flip-flop pairs used |
108 |
|
|
No. with an unused flip-flop |
108 out of 108 |
100% |
|
No. with an unused LUT |
0 out of 108 |
0% |
|
No. of fully used LUT-FF pairs |
0 out of 108 |
0% |
|
No. of unique control sets |
0 |
|
|
No. of IOs |
31 |
|
|
No. of bonded IOBs |
31 out of 232 |
13% |
|
No. of
DSP48A1s |
1 out of 32 |
3% |
