2 bit multiplier
2 BIT MULTIPLIER:
VHDL CODE
Design of 2 bit Multiplier:
library ieee;
use ieee.std_logic_1164.all;
entity AND2 is
port(
A,B: in BIT;
x : out BIT);
end AND2;
architecture behavioral of AND2 is
begin
x <= A and B;
end behavioral;
entity half_adder is
port (a, b : in BIT;
sum, carry : out BIT
);
end half_adder;
architecture arch of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end arch;
entity multiply_struct is
port (A, B : in bit_vector(1 downto 0);
P : buffer bit_vector(3 downto 0)
);
end multiply_struct;
architecture structural of multiply_struct is
component AND2
port(
A,B: in BIT;
X : out BIT);
end component;
component half_adder
port (A, B : in BIT;
sum, carry : out BIT);
end component;
signal S1,S2,S3,S4:BIT;
begin
A1: AND2 port map(A(0),B(0),P(0));
A2: AND2 port map(A(1),B(0),S1);
A3: AND2 port map(A(0),B(1),S2);
A4: AND2 port map(A(1),B(1),S3);
H1: half_adder port map(S1,S2,P(1),S4);
H2: half_adder port map(S4,S3,P(2),P(3));
|
TESTBENCH OF 2 bit Multiplier: |
library ieee;
use ieee.std_logic_1164.all;
entity multiply_behav_tb is
end multiply_behav_tb;
architecture tb of multiply_behav_tb is
component multiply_behav is
port (A, B : in bit_vector(1 downto 0);
P : out bit_vector(3 downto 0)
);
end component;
signal A, B : bit_vector(1 downto 0);
signal P : bit_vector(3 downto 0);
begin
UUT : multiply_behav port map (
A => A,
B => B,
P => P);
Force:process
constant period: time := 20 ns;
begin
A <= "00";
B <= "00";
wait for period;
A <= "00";
B <= "01";
wait for period;
A <= "00";
B <= "10";
wait for period;
A <= "00";
B <= "11";
wait for period;
A <= "01";
B <= "00";
wait for period;
A <= "01";
B <= "01";
wait for period;
A <= "01";
B <= "10";
wait for period;
A <= "01";
B <= "11";
wait for period;
A <= "10";
B <= "00";
wait for period;
A <= "10";
B <= "01";
wait for period;
A <= "10";
B <= "10";
wait for period;
A <= "10";
B <= "11";
wait for period;
A <= "11";
B <= "00";
wait for period;
A <= "11";
B <= "01";
wait for period;
A <= "11";
B <= "10";
wait for period;
A <= "11";
B <= "11";
wait for period;
wait;
end process;
end tb;
RTL SCHEMATIC:
